Staff FPGA Engineer

Company Overview

Ambiq's mission is to develop the lowest-power semiconductor solutions to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world. Ambiq has helped leading manufacturers worldwide develop products that last weeks on a single charge (rather than days), while delivering a maximum feature set in compact industrial designs. Ambiq's goal is to take Artificial Intelligence (AI) where it has never gone before in mobile and portable devices, using Ambiq's advanced ultra-low power system on chip (SoC) solutions. Ambiq has shipped more than 250 million units by 2024. For more information, visit www.ambiq.com.

Our innovative and fast-moving teams of research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin and San Jose), Taiwan (Hsinchu), China (Shenzhen and Shanghai), Japan (Tokyo), and Singapore. We value continued technology innovation, fanatical attention to customer needs, collaborative decision-making, and enthusiasm for energy efficiency. We embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies. We encourage and nurture an environment for growth and opportunities to work on complex, engaging, and challenging projects that will create a lasting impact. Join us on our quest for 100 billion devices. The endpoint intelligence revolution starts here.

Scope

As the Staff FPGA Engineer at Ambiq, you will drive the development and rendering of FPGA images in support of our pre-silicon prototyping environments. 

In this role, you will work with our SoC design, software development, design verification, and system test teams as our primary internal customers for the FPGA images. 

The successful candidate will have experience in RTL design, verification, and FPGA/Prototyping platform creation to support Design Verification, Validation, Software Development and System Test at the pre-silicon phase. 

The person in this role must be comfortable in working with RTL in order to provide specialized changes to the SoC database specific to the FPGA development flow. This role will require defining and implementing internal and external FPGA timing constraints to enable repeated delivery of design iterations to the software and validation teams. The candidate will be required to debug RTL designs using FPGA tools, external logic analyzers, and protocol analyzers.

Responsibilities

• Implement and debug FPGA designs on AMD FPGA based prototyping platforms using Xilinx Vivado and ISE tools.
• Implement and debug FPGA designs on a Stratix-10 development board using Intel Quartus prime Pro. 
• Support a regression test-suite consisting of system-level test cases to validate updated FPGA builds. 
• Assist development teams in reproduction, triage, and debug of issues both pre-silicon and post-silicon
• Define and implement timing constraints.

• BSEE or BSCE with 10+ years of SoC design, verification, or related work experience and 8+ years of experience of FPGA design, bring-up, debugging, and verification.
• In-depth knowledge of top-down FPGA development process with recent experience with FPGA-based prototyping on an FPGA development platform.
• Solid experience with defining timing constraints for Static Timing Analysis.
• Some familiarity with Cadence SoC design flow.
• Expertise in both Intel Quartus Prime Pro and Xilinx Vivado suites.
• Solid understanding of the tool flow from RTL to bitstream.
• Some familiarity with programming in C language.
• Familiarity with source code control systems (git) required.
• Familiarity with simulation tools.
• Hands-on lab bring-up experience, debug, and instrument usage.

In addition, the following areas of experience are highly desirable for the position but not strictly required:

• In-depth experience with Stratix 10 FPGA platforms: boards, debug, performance, and throughput tuning.
• In-depth experience with AMD VU19P prototyping systems, debug, design partitioning, performance, and throughput tuning.
• Experience with low power designs.
• Experience with embedded microprocessors.
• Proven design validation skills.
• In-depth experience writing Verilog code.
• Experience with System Verilog verification environments.
• Good analytical skills.
• Python script experience.
• YAML
• Peripheral protocols: I2C, I3C, MSPI, UART, USB

What You'll Need:

The successful candidate must be self-motivated, creative, and comfortable learning exciting new technologies. This is an opportunity for growth and work on complex, interesting, and challenging projects. 

Most importantly, the successful candidate will be able to live the Ambiq Shared Values:

• Innovate: We tenaciously find ways to break down the barriers to possible solutions
• Collaborate: We proactively communicate and encourage each other to be better.
• Focus: We keep the voice of the customer at the center of everything we do.
• Learn: We strive for continuous improvement and are always curious.
• Achieve: We execute on quality and follow through on our commitments.