ASIC Verification Engineer
Uni Connect
Full-time
On-site
Singapore, R, Singapore
Manufacturing & Production
- As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state -of -the -art verification methodologies in ever -increasing design complexities, from UVM, C/C++ co -simulation, system emulation to mixed -mode simulation & formal verification. The goal is simple – to achieve zero -defect with the best and smartest approach to the large verification space.
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<\/div><\/span>Requirements<\/h3>
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<\/div>Requirements<\/b><\/span>
<\/p><\/span>- Experience in UVM verification methodology.
<\/li><\/span>- Disciplined, quality -minded, and highly driven for excellence.
<\/li><\/span>- Excellent team player and good communication skills.
<\/li><\/span>- MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience, but are open to fresh graduates with outstanding results.
<\/li><\/span>- Candidates with relevant experiences would be offered as Senior or Staff, taking on higher responsibilities.
<\/li><\/span>- Experience in video processing and video analytics is a plus.
<\/li><\/span>- Passionate and strong in general programming is a plus.
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<\/div><\/span> - Disciplined, quality -minded, and highly driven for excellence.
- Experience in UVM verification methodology.