Participate in high-level product specifications, microarchitecture and implementation of high-speed memory interfaces
Responsible for delivery of AMS circuits in SerDes, including the evaluation of different circuit topologies
Worked on high-speed serial and parallel interface design, defining specifications and implementing modules such as bandgap, bias circuits, LDO regulators, amplifiers, comparators, switched capacitor circuits, ADCs, DACs, oscillators, filters, Tx/Rx equalization techniques and circuits such as de-emphasis, CTLE, DFE, CDR architecture and implementation, high-speed digital circuits (serializers, deserializers, counters, dividers, etc.)
Work with the verification team for lab debugging
Work with the software team and/or customers to solve problems, debug and tune system performance
Requirements
Bachelor's degree in communications, electronic engineering or computer engineering, master’s degree preferred
More than 4 years (senior engineer) and 6 years (staff engineer) of ASIC design experience, familiar with ASIC development process
Good AMS circuit design skills and EDA tools such as Cadence Virtuoso, Calibre, Hspice/Spectre, and static timing analysis tools (e.g., Nanotime)
Familiarity with high-speed interfaces such as DDR, SerDes, PCIe is preferred
Ability to solve customer problems and deliver results in a timely manner
Strong organizational and communication skills where English is a must and Chinese is preferred