Responsible for high quality, on-time tapeouts with good influencing, driving collaboration skills.
Drive Interlock meeting between functions. Collaborate closely with Arch, SW, validation and product/application teams.
Attract and retain a world class team of RTL and DV engineers. Define team objectives and outcomes; enable success across boundaries; Help the team adapt and learn
Have keen eye to details across various chip design & implementation functions.
Budget & Resource management working with functional leads and exec management.
Keen in establishing processes and automation that ensures quality and enable reliable tapeouts
Support SOC Design, Physical Design, Design Verification, Post-Si org.
Track Design Metrics etc and generate relevant data for SoC org for tracking purposes.
Drive Lesson Learnt for SOC org and drive closure of action items
Schedule different design reviews (HLDR, MLDR, LLDR etc)
Goals tracking for team: Tracking and reporting Goals
Interact and support customers as needed to debug any issues or product presentations
Requirements
Requirements
Education Requirements: Minimum requirement for this position is Bachelors in EE or CS.
Must have overall 15+ year of experience in the Chip Design and Management. Preferably having experience in Microarchitecture, RTL design, DV and Chip Program Management
Have worked in end to end of SoC design to tapeout experience.
Should be familiar with Design EDA tools for Synthesis, power (CLP), Constraints Verification.