Implement and debug FPGA designs on AMD FPGA based prototyping platforms using Xilinx Vivado and ISE tools.
Implement and debug FPGA designs on a Stratix-10 development board using Intel Quartus prime Pro.
Support a regression test-suite consisting of system-level test cases to validate updated FPGA builds.
Assist development teams in reproduction, triage, and debug of issues both pre-silicon and post-silicon
Define and implement timing constraints.
Requirements
BSEE or BSCE with 10+ years of SoC design, verification, or related work experience and 8+ years of experience of FPGA design, bring-up, debugging, and verification.
In-depth knowledge of top-down FPGA development process with recent experience with FPGA-based prototyping on an FPGA development platform.
Solid experience with defining timing constraints for Static Timing Analysis.
Some familiarity with Cadence SoC design flow.
Expertise in both Intel Quartus Prime Pro and Xilinx Vivado suites.
Solid understanding of the tool flow from RTL to bitstream.
Some familiarity with programming in C language.
Familiarity with source code control systems (git) required.
Familiarity with simulation tools.
Hands-on lab bring-up experience, debug, and instrument usage.
In addition, the following areas of experience are highly desirable for the position but not strictly required:
In-depth experience with Stratix 10 FPGA platforms: boards, debug, performance, and throughput tuning.
In-depth experience with AMD VU19P prototyping systems, debug, design partitioning, performance, and throughput tuning.
Experience with low power designs.
Experience with embedded microprocessors.
Proven design validation skills.
In-depth experience writing Verilog code.
Experience with System Verilog verification environments.